Shared Bus Cache Coherency (cont)
Only way to get to Shared Modified state if using a Write Invalidate policy:
- Processor A has cache line Exclusive Modified
- Processor B has a read miss on the same cache line, issues a coherent read on the bus
- Processor A responds to the coherent read by supplying the cache line to Processor B
- The cache state in Processor A and Processor B becomes Shared Modified