Shared Bus Cache Coherency

• Recall the discussions on HyperSparc cache coherence over a shared bus

  • Five Cache line States: Invalid, Exclusive Clean, Exclusive Modified, Shared Clean, Shared Modified
  • Used 3 bits: V (valid), S (shared), M (modified)

• Write Invalidate Policy meant that if Processors A, B, C all has data which is consistent with Memory(Shared Clean state), and processor A writes to data, then cache lines in Processors B, C are invalidated, and Processor’s A becomes Shared Modified

  • Alternative is to broadcast data over bus to processors B,C (write broadcast policy)

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