Caveats on Branch Delay Slots
Deeply pipelined (SuperPipelined) machines may have more than one branch delay slot
- Becomes harder for compiler to find useful instructions to go in delay slots
Branch Delay slots have to be defined in the Instruction Set Architecture (ISA)
- The X86 ISA did not define branch delay slots, so pipelined implementations could not make use of this approach
- Simply have to stall the pipeline
- Make every attempt to compute the branch target address and check the branch condition as EARLY AS POSSIBLE in the pipeline.