Delay Slots and SuperScalar/VLIW Machines
SS or VLIW fetches N instructions at a time (the branch instruction + N-1 other instructions.
The next N instructions are in the branch delay slot.
Essentially have 2N-1 instructions in a single branch delay slot!!
- Very hard for compiler to find 2N-1 useful instructions!
- As N grows, problem gets worse
Bottom Line: Delay Slot approach not viable for aggressive SS or VLIW machines
- Must look for a different solution