Selecting between two input signals is a common operation. Many conditional VHDL statement will generate a multiplexer to choose between different input sources:
IF (sel = '0') THEN out <= signal_0; ELSE out <= signal_1; END IF;
But multiplexers can also be introduced with other constructs, where it is less obvious. For example, choosing a particular input source with an index will normally generate a multiplexer (figure 2). These multiplexers grow with the number of input signals and signal width.
Multiplexers are expensive to implement in FPGAs, as their implementation requires many CLBs and routing resources. An alternative method of selecting an input signal from several options is to use a tri-state bus (see figure 4). This method is advantageous on Xilinx FPGAs, as tri-state buffers and tri-state buses (in the form of longlines) are already integrated on the chip [Wal95].
Tristate devices can be generated using the following assignment:
bus <= value WHEN enable ELSE (Others => 'Z');
Figure 1: Entity declaration for select.
Figure 2: Signal selection using a multiplexer.
Figure 3: Signal selection using a tri-state
bus.
Figure 4: Multiplexer and equivalent three-state
logic.
Using tristate drivers, a similar signal selection can be implemented with a tristate bus (see figure 3). Depending on the FPGA part, Xilinx supports between 16 and 64 three-state busses (``longlines'') per chip and between 10 and 34 tri-state buffers per longline. If these longlines are not used by any other circuitry, using them for signal selection allows to pack more functionality in a single FPGA.
Depending one the number of input sources and input width, different implementations may optimize either resource usage or timing. In the XC4000 series, a 4:1 multiplexer can be implemented using a single CLB, leading to minimal timing. Larger multiplexers exceed the capacity of a single FPGA, and as the number of inputs increases, tri-state solutions offer competitive timing.
Especially for wide signals or a large number of input sources, a tri-state based selection method reduces CLB usage drastically. No combinatorial logic is necessary to select the input, instead only the select signal is decoded to drive tri-state buffers which flank each CLB. For narrow signals (1 or 2 bits), CLB usage is comparable.
For wider signals, a selection mechanism based on tri-state
functionality is preferable: the tristate implementation uses a
fixed number of CLBs for generating tri-state buffer control
signals, and a tri-state buffer for each signal bit, i.e. 
tri-state devices (n
being the number of signals, w the width of the signal in
bits). Often, these tri-state resources are unused, so this
implementation increases overall FPGA resource utilization.
Tables 4 and 5 compare the FPGA resource
usage for signal selection using multiplexers and tristate
buffers, respectively.
Table 4: This table shows the number of CLBs
required for selecting an output signal with multiplexing logic,
as a function of the number of input signals and signal width.
These results were reported by FPGA compiler 3.1a.
Table 5: This table shows the number of CLBs and
tristate buffers required for selecting an output signal using a
tristate bus, as a function of the number of input signals and
signal width. These results were reported by FPGA compiler 3.1a.
One caveat is the number of tri-state resources (buffers and longlines) which are available and their connectivity. Since the connectivity of tri-state buffer elements (TBUF) is fixed, and there is a limited number of longlines, there are upper bounds as to the size of the tri-state select mechanism. For example, the XC4010 has 40 longlines and 22 TBUFs per longline, restricting the select mechanism to a width of 40 bits (if all longlines are dedicated to a single select) and the output can be selected from a maximum of 22 signals. (In the XC4000 series, horizontal longlines can be split, so the XC4010 can also be configured as having up to 80 longlines with 11 TBUFs per longline.)
The choice of output selection mechanism has a significant influence on the size of all blocks where signals have to be selected, e.g. register files.
