The generation of state machines is another area where conventional ASIC synthesis and FPGA synthesis differ. When ASICs are the target technology, fully encoded representations such as binary or gray code encoding of states lead to space efficient designs, whereas the faster one-hot encoding scheme consumes more resources [Syn95d].
This is different in FPGA designs, where the state decoding logic for decoding a binary encoding would consume many CLBs, while many flip-flops on the same die go unused! Thus one-hot encoding is not only much faster, but also the more compact representation [AN94].
Table 3: Resource usage for FSM compilation
using different encoding schemes and optimization constraints.
These results were reported by FPGA compiler and design compiler,
respectively (version 3.1a).
Table 3 gives the synthesis results of a simple finite state machine for the Xilinx XC4000 series and the LSI 10k ASIC library [Syn95c]. The table compares four encoding techniques available in Synopsys: one-hot encoding, a solution adapted to the particular FSM (auto), gray code encoding, and binary encoding of states.
The one-hot encoding scheme uses 6 flip-flops for state encoding, while all other implementations use 3. Although this leads to significantly larger ASIC implementations, the FPGA FSM implementation is comparable to the smallest solution. While the optimal encoding always depends on the particular state machine being used, for most state machines one-hot encoding is superior for FPGA implementations. One-hot encoding not only is the fastest encoding, but also one of the smallest representations because it exploits the availability of many flip-flops on an FPGA.
In some tools, VHDL source level encoding of the state vector may be necessary to achieve this. Synopsys supports the extraction of state machines from a design and to define an encoding to be used for the state vector. This approach is advantageous, since several different encodings can be tested and compared without having to modify the source code.