The primary Unix-based tools used were Viewlogic, Synopsys, and Xilinx XDM.
Viewlogic's Powerview ABEL compiler (ViewPLD) was used to create JEDEC programmer files from the GAL source files written in ABEL. ViewPLD also creates simulatable timing models of the GALs as well as pinout drawings. The Powerview schematic editor, ViewDraw, and simulator, ViewSim, were used to test the design of Rocky before construction. As an alternative to translating ABEL files using the graphical interface tools, the Viewlogic command line tools were used to facilitate use of a Makefile and operation from non-graphics terminals. These tools are described in Appendix B.
The Synopsys, and Xilinx tools were used primarily towards producing the synthesizable VHDL file for the FPGA. Mentor's Design Architect program was also used to create a simulatable counter circuit for educational purposes, and Mentor's VHDL compiler was used to produce a simulatable VHDL model of the 62256 SRAM chip used in the project.
The Synopsys and Xilinx tools were used to translate VHDL source code into both simulatable ViewSim files and downloadable Xilinx BIT files. This process is described in Appendix C.
On the PC, the Borland C++ compiler and debugger were used to create and debug the staller, download, and other programs. The DOS DEBUG program proved to be useful for quick-and-dirty port I/O tests in conjunction with a handheld logic probe. For more serious timing analysis, the HP logic analyzer was used to display signals such as the FPGA configuration signals.