The software versions currently installed at Duke are Synopsys Design Compiler v3.2b and Xilinx 5.1.0 tools, with the Xilinx/Synopsys Interface (XSI) libraries. These versions are vastly better than previous versions and seem to work flawlessly toegether. For previous versions I had figured out complicated file dependencies and hunted for appropriate libraries, command-line options, and file formats. Now that XMAKE and XSIMMAKE work so seamlessly with Viewlogic and Synopsys output, the designer needs to know far fewer picky details.
The process described in this tutorial is automated entirely (along with lots of other stuff like printing and archiving) by my Makefile; see Appendix C.1 below.
The first stage in the process is to create VHDL files in a format that Synopsys likes. There are some differences between this and the format that Viewlogic VHDL Analyzer uses, and we would like to be able to switch to either format so that Viewsim can still be used to perform functional simulation. My method is to pass each VHDL source file through the C preprocessor with either vhdl_vl.h or vhdl_syn.h prepended. These header files perform a crude conversion between VHDL formats on the fly; see Appendices C.2 and C.3.
The second stage is to synthesize logic from VHDL, saving the results to a SEDIF netlist interchange file. In the early stages of your design you should run Synopsys Design Analyzer ( design_analyzer), a tool in which you can read each of your VHDL files, compile, and view the synthesized logic and critical paths graphically. However, to get down to business you should gather all your commands into a script file; in fact, all the menu-driven operations supprted in Design Analyzer generate commands which are dumped into a file called command.log which you can use as a starting point. Refer to Appendix C.4 for a listing of my script, boris.dcsh, which you can run non-interactively with the command dc_shell -f boris.dcsh.
While the Synopsys Design Compiler saves its internal information about your design in DB files, you must export the design in SEDIF format for use by the Xilinx tools.
The Xilinx program XMAKE starts with either a SEDIF file from Synopsys or with a Viewdraw WIR netlist file. For an XC3000 design, XMAKE first runs either syn2xnf or wir2xnf, followed by xnfmerge, xnfprep, xnfmap, map2lca, apr, and makebits. For an XC4000 design using XBLOX, it runs xnfmerge, xnfprep, xblox, xnfprep (again), ppr, and makebits. The tools should all be run from the XDM environment to make life easier.
An extremely useful Xilinx tool is the XSIMMAKE program, accessible from XDM. This program uses the XMAKE output (LCA file), back-annotates an XNF file with post-routing delay information, and runs xnf2wir to produce a Viewlogic netlist (WIR) file and a ViewSim VSM file. This allows you to simulate the placed and routed design with realistic timing values.
The resulting LCA layout can be viewed using the XDE Editlca program. It is interesting to view the CLBs which were generated for your logic, although not necessary.