ABEL is a logic description language which allows state diagram descriptions and test vectors. This document describes the process of translating an ABEL source file into both a simulatable ViewSim file and a programmer JEDEC file, using the command-line tools only. This is nothing too revolutionary, the same thing can be done using the ViewPLD graphical tool, and this has been described well in the Powerview Tutorial [1]. This is also not a tutorial of the ABEL language; perhaps the best way to learn ABEL is to look at and modify existing ABEL files.
The first step is to enable the command-line Powerview environment, which simply involves setting the WDIR environment variable and some paths in your .cshrc file. Obviously these settings are system-dependent and subject to change.
setenv WDIR ~/powerview/standard:/opt/digital/share/powerview2/standard set path = ($path /opt/digital/share/powerview2 /opt/digital/bin)
The alternate method is to simply type /opt/digital/bin/powerview to run the tools from the Powerview Cockpit.
The tools used in the process are ahdl2pla, plaopt, devsel, fuseasm, pla2view, and j2vhdl. This is not an attempt to describe what each tool does. That can be found in the ViewLogic documentation, and much can be learned about the tools by typing the program name without any arguments.
The best way to describe the arguments, dependencies, and output of each tool is a Makefile. The PROJ variable contains the name of the project, which must be 8 characters or less and should match the module name in the source file.
Correct errors by editing the ABEL source file in the original directory. To program the GAL, copy the JEDEC file ( .jed) to a machine with a PLD programmer using a diskette or ftp. For the JDR programmers and the AMD PALCE22V10H part, use the program GAL2 to program the chip.
Test vectors provide an excellent way to test the logic at the design entry, simulation, and chip levels. Simply thinking what the values in the test vectors should be provides a valuable check of whether the logic is fundamentally sound. The j2vhdl program shown in the Makefile above produces a ViewSim command file ( .cmd). A simple, text-interface way to check the logic is to type viewsim -nographics proj -proj.cmd, and browse the output for statements such as ``Output Z does not match '0' at time T!''
Once you've programmed the chip itself, you can verify that it actually works by running PALTEST on the PC. The JEDEC file has the test vectors stored in it, so point PALTEST to the JEDEC file and test the chip once or in a loop.