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In Verilog HDL, you can use a Gate Instantiation to insert an instance of a Verilog HDL gate primitive into your Verilog Design File (.v). (Quartus^® II primitive instantiation is described in Using a Quartus II Logic Function.) A Gate Instantiation connects gate primitive terminals to the signals or interface port of the associated module. Gate primitives are built into the Verilog HDL, and are described in "Section 7: Gate and Switch Level Modeling" of the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.

For information about Quartus II support for gate primitives, go to Gates & Switches.

In the example below, two Gate Instantiations create instances of and gate and not gate primitives.

module gateinst (a, b, c, d, x, y); 

    input   a, b, c, d; 
    output  x, y;

    and and1 (x, a, b, c);

    not not1 (y, d);

endmodule

In the and Gate Instantiation, the values x, a, b, and c are mapped to the corresponding terminals of the gate primitive. The connection to the output terminal is listed before the connections to the input terminals.

In the not Gate Instantiation, the connection to the output terminal is listed before the connection to the input terminal, i.e., the output terminal is mapped to y, and the input terminal is mapped to d.

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