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Reports state machine assignments made by the Logic Synthesizer for a SignalTap^® II File (.stp), or a Text Design File (.tdf).

The values of the state bits for each state of a state machine are reported in the AHDL State Machine Declaration format. This section is omitted if the project does not contain state machines. The table in the section represents one state machine with the names of the states, and the values for each of the encoded bits in the states.

The following example shows a State Machines section for a sample design:

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