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A state machine is a sequential circuit that advances through a number of states. To describe a state machine in Quartus® II VHDL, you can declare an enumeration type for the states, and use a Process Statement for the state register and the next-state logic.
The VHDL example shown below implements a 3-state state machine.
ENTITY state_machine IS
PORT(
clk : IN STD_LOGIC;
input : IN STD_LOGIC;
reset : IN STD_LOGIC;
output : OUT STD_LOGIC_VECTOR(1 downto 0));
END state_machine;
ARCHITECTURE a OF state_machine IS
TYPE STATE_TYPE IS (s0, s1, s2);
SIGNAL state : STATE_TYPE;
BEGIN
PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
state <= s0;
ELSIF (clk'EVENT AND clk = '1') THEN
CASE state IS
WHEN s0=>
IF input = '1' THEN
state <= s1;
ELSE
state <= s0;
END IF;
WHEN s1=>
IF input = '1' THEN
state <= s2;
ELSE
state <= s1;
END IF;
WHEN s2=>
IF input = '1' THEN
state <= s0;
ELSE
state <= s2;
END IF;
END CASE;
END IF;
END PROCESS;
PROCESS (state)
BEGIN
CASE state IS
WHEN s0 =>
output <= "00";
WHEN s1 =>
output <= "01";
WHEN s2 =>
output <= "10";
END CASE;
END PROCESS;
END a;
This state machine includes a Process Statement that is activated on every positive edge of the
clk control signal for the next-state logic, and a Process Statement that is activated on a change in the state variable. This state machine has an asynchronous reset, which the Compiler recognizes.
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The Compiler also recognizes state machines with a synchronous reset. |
The signal state stores the current state of the state machine. The declaration of the type
STATE_TYPE defines the states s0, s1, and s2 for state_machine.
At startup, the state machine is initialized to the reset state. If there is no reset state, the state machine is initialized to the first state in the Type Declaration. Otherwise, the first Case Statement determines the transitions between the states (that is, which state to enter on the next rising edge of clk) and the second Case Statement determines the value of the outputs for each state.
The Compiler recognizes state machines and reports them as such in the State Machines section of the Compilation Report only if all of the following conditions are met:
The Process Statement that describes the state machine must be clocked, and must
contain an If Statement that checks for a positive edge of the clk control signal.
The state machine behavior, that is, the next-state logic, is defined with Case Statements at the top level.
All assignments to the signal or variable that represents the state machine are within the process.
No If Statement that is a function of the state variable can assign to the state variable. Case Statements should be used instead. Example
The state machine must have more than two states.
VHDL state machines that do not meet these conditions are converted into logic gates and
registers that are not listed as state machines in the Compilation Report. The Compiler also converts
VHDL state machines to "regular" logic when the ENUM_ENCODING attribute is used to manually
specify state assignments in a project.
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Because the Compiler usually produces the best results, Altera®
recommends that you do not use the ENUM_ENCODING attribute, but instead allow the
Compiler to recognize and encode the state machine. |
You can assign states in the following ways:
For more information, see the following sections of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual:
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