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A latch can be implemented implicitly with a Register Inference. The Quartus^® II software can infer a latch from If Statements that have not been completely specified. The If Statement should be inside a Process Statement.

The following example shows a VHDL Design File (.vhd) that includes a Process Statement with an If Statement that has not been completely specified.

ENTITY latchinf IS
   PORT
   (
      enable, data    : IN STD_LOGIC;
      q               : OUT STD_LOGIC
   );
END latchinf;

ARCHITECTURE maxpld OF latchinf IS
BEGIN

latch :	PROCESS (enable, data)
      BEGIN
         IF (enable = '1') THEN
            q <= data;
         END IF;
      END PROCESS latch;

END maxpld;

In this example, the circuit analyzes the value of the enable signal. If enable equals '1', the value data is assigned to q. If enable equals '0', the circuit maintains its previous state, creating a latch.

For more information, see the following sections of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual:

• Section 8.6: If Statement
• Section 9.2: Process Statement

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