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Lists usage information about the PLLs in Cyclone™ devices and the enhanced PLLs and fast PLLs in Stratix™ and Stratix™ GX devices. This section reports the values of the specific output clock(s) for the PLLs in the design. This section is omitted if the Cyclone design does not include PLLs or the Stratix design does not include enhanced or fast PLLs.
Information is provided as follows:
| Heading | Description | Value |
|---|---|---|
| Name | Shows the instance name of the PLL. | <PLL instance name> |
| Output clock | Shows the output clock you specified for the PLL. | <clock name> |
| Mult | Shows the multiplication factor for the PLL output clock. | <value> |
| Div | Shows the division factor for the PLL output clock. | <value> |
| Output Frequency | Shows the clock frequency value for the PLL output port. This value is equal to the input frequency multiplied by the multiplication factor for the PLL output port, and divided by the division factor for the PLL output port. | <frequency> MHz |
| Phase Shift | Shows the value you specified for the phase shift of the PLL output clock, measured in picoseconds (ps). | <time> ps |
| Delay | Shows the time delay you specified for the PLL output clock, measured in picoseconds. | <time> ps |
| Counter | Shows the counter value you specified for the PLL output clock. | L0 | L1 | G0 | G1 | G2 | G3 | E0 | E1 | E2 | E3 | M | N |
| Counter delay | Shows the counter delay you specified for the PLL output clock, in picoseconds. | <time> ps |
| Counter Value | Shows the counter value for the PLL. This value is equal to the sum of the high and low cycles specified for the PLL. Bypass is shown if there are no high or low cycles specified for the PLL. | <counter value> | Bypass |
| High / Low | Shows the number of high and low cycles for the PLL. | <high cycles> / <low cycles> Even | Odd |
| Initial | Shows the initial counter value for the PLL output clock. | <counter value> |
| VCO Tap | Shows the VCO tap value for the output clock. | 0 | 45 | 90 | 135 | 180 | 225 | 270 | 315 |
The following example shows a portion of the PLL Usage section generated for a sample design:
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