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Lists information about the PLLs in Cyclone™ devices and the enhanced PLLs and fast PLLs in Stratix™ and Stratix™ GX devices. This section is omitted if the design does not include PLLs.
Information is provided for each PLL instance as follows:
| PLL Property | Description | Value |
|---|---|---|
| PLL type | Shows the type of PLL. | Enhanced | Fast | Auto |
| Scan chain | Shows the value specified for the scan chain option. | None | Long | Long(unused) | Short | Short(unused) |
| PLL mode | Shows the mode in which the PLL is operating. | Normal | Zero delay buffer | No compensation | External feedback |
| Feedback source | Shows the feedback source for the PLL. | ExtClk0 | ExtClk1 | ExtClk2 | ExtClk3 |
| Compensate clock | Shows the mode of the PLL compensate clock. | Clock0 | Clock1 | Clock2 | Clock3 | Clock4 | Clock5 | Global clock | Regional clock | Diffio clock | ExtClock0 | ExtClock1 | ExtClock2 | ExtClock3 |
| Switchover on loss of clock | Shows whether the switchover on loss of clock was turned on for the PLL. | on | off |
| Switchover on gated lock | Shows whether switchover on gated clock was turned on for the PLL. | on | off |
| Switchover counter | Shows the value of the PLL switchover counter. | <counter value> |
| Primary clock | Shows which clock acts as the primary clock for the PLL. | <clock name> |
| Input frequency clock0 | Shows the input frequency for input clock 0 in megahertz. | <input frequency> MHz |
| Input frequency clock1 | Shows the input frequency for input clock 1 in megahertz. | <input frequency> MHz |
| Nominal VCO frequency | Shows the value of the minimal VCO frequency for the PLL in megahertz. | <frequency>MHz |
| Freq min lock | Shows the minimum lock frequency for the PLL in megahertz. | <frequency>MHz |
| Freq max lock | Shows the maximum lock frequency for the PLL in megahertz. | <frequency>MHz |
| Hold conf done | Shows whether the QUALIFY_CONF_DONE parameter was turned on for the PLL. |
on | off |
| M value | Shows the value of the M counter | <counter value> |
| N value | Shows the value of the N counter | <counter value> |
| M counter delay | Shows the delay value for the M counter. | <time> ps |
| N counter delay | Shows the delay value for the N counter. | <time> ps |
| M2 value | Shows the spread spectrum modulus for the M counter. | <modulus value> |
| N2 value | Shows the spread spectrum modulus for the N counter. | <modulus value> |
| SS counter | Shows the value for the spread spectrum counter for the PLL. | <counter value> |
| Downspread | Shows the downspread percentage for the PLL in megahertz. | <downspread percentage> % |
| Spread frequency | Shows the spread frequency for the PLL in megahertz. | <frequency> MHz |
| Charge pump current | Shows the charge pump current value for the PLL in microamperes. | <current> uA |
| Loop filter R | Shows the value for the loop filter R resistor in ohms. | <value> Ohm |
| Loop filter C | Shows the value for the loop filter C capacitor in picofarads. | <value> pF |
| F zero | Shows the frequency of F zero for the PLL. | <frequency> MHz |
| Bandwidth | Shows the bandwidth value for the PLL in megahertz or kilohertz. | <frequency> MHz | KHz |
| F pole | Shows the frequency of F pole for the PLL in megahertz. | <frequency> MHz |
| Enable0 counter | Shows which PLL counter is used by the enable0 input port of DIFFIOCLK. | <counter value> |
| Enable1 counter | Shows which PLL counter is used by the enable1 input port of DIFFIOCLK. | <counter value> |
| Real time configurable | Shows whether the real time configuration option was turned on for the PLL. | on | off |
| Bit stream for reprogramming | Shows the hexadecimal bit stream needed for reprogramming the PLL in real time. The bit stream should be shifted in from left to right: the first bit to shift in is the left-most bit shown in the bit stream for reprogramming value. The direction in which the bit stream needs to be shifted into the PLL is included in the right hand side of the bit stream value. The transfer enable bit is included in the bit stream value and is logic level high and shifted in first (for example, the left-most bit of the bitstream is always a value of one). | <bit stream value> |
The following example shows a portion of the PLL Summary section generated for a sample design:
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- PLDWorld - |
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