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MegaLAB Usage Summary Section (Compilation Report)



Displays summary information about how each MegaLAB structure in the device uses available resources.

This section only occurs if you specify an APEX 20K, APEX II, or ARM®-based Excalibur device for compilation.

Information is provided as shown in the the following table:


Heading Description
MegaLAB Name Shows the MegaLAB name, which identifies its location in the device.
Total Cells Shows the total number of logic cells in the MegaLAB structure.
MegaLAB Interconnect Lines Shows the number of MegaLAB interconnect lines used in the MegaLAB structure.
Column Fast Lines Driving In Shows the number of lines in the column interconnect channels that are driven in by the logic cells in the MegaLAB structure.
Column Fast Lines Driving Out Shows the number of lines in the column interconnect channels that are driven out by the logic cells in the MegaLAB structure.
Row Fast Lines Driving In Shows the number of lines in the row interconnect channels that are driven in by the logic cells in the MegaLAB structure.
Row Fast Lines Driving Out Shows the number of lines in the row interconnect channels that are driven out by the logic cells in the MegaLAB structure.
Fan-In Shows the total fan-in from the row and column fast lines.
Fan-Out Shows the total fan-out from the row and column fast lines.
Local Lines Shows the total number of local lines used in the MegaLAB structure.
LAB External Interconnect Shows the number of LAB external interconnects (that is, lines in the local interconnect region that are driven by signals transferred between logic elements in non-adjacent LABs) used in the MegaLAB structure.
Control Signals Shows the total number of control signals used in the MegaLAB structure.

 

The following example shows a MegaLAB Usage Summary section of a sample design:


MegaLAB Usage Summary Section (Compilation Report)

 

MegaLAB Usage Summary Section (Compilation Report)


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