See Also

Lists the resource usage of the following resources for each LogicLock^™ region in the design: LogicLock region name, origin, width, height, logic cells, registers, memory bits,, DSP block sub-blocks, the number of DSP block 9x9, 18x18 and 36x36 multipliers, virtual pins, and logic cell usage (logic cells that only utilize the LUT in the logic cell, logic cells that only use the register, and logic cells that use both register and LUT). The specific resources listed in the Compilation Report may vary depending on the device selected. Resource usage is calculated after fitting.

The Logic Cells, LUT-Only LCs, Register-Only LCs, and LUT/Register LCs columns list the logic cells used by the design entity and, if applicable, the number of logic cells instantiated by the design entity.

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