Report Window

All Package Pins Section (Compilation Report)

Lists all the pins and their I/O standards for the target device package.

The pin name and the symbol in the pin name represent the type of pin and its function as follows:

Pin Name or Symbol in Name Description
N.C. No Connect. This pin has no internal connection to the device.
VCCINT Dedicated power pin, which must be connected to VCC Internal.
VCCIO Dedicated power pin, which must be connected to VCC I/O.
VCC_PLL Dedicated power pin associated with ClockLock® circuitry. This pin name does not appear if the design does not contain a ClockLock PLL.
GND Dedicated ground pin or unused dedicated input, which must be connected to GND.
GND_PLL Dedicated ground pin associated with the ClockLock circuitry. This pin name does not appear if the design does not contain a ClockLock PLL.
GNDINT Dedicated ground pin or unused dedicated input, which must be connected to GND.
GNDIO Dedicated ground pin, which must be connected to GND.
RESERVED Unused I/O pin, which must be left unconnected.
^ character in name Dedicated configuration pin.
+ character in name Reserved configuration pin that is tri-stated during user mode.
* character in name Reserved configuration pin that drives out in user mode.
# character in name JTAG BST/in-system programming or configuration pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& character in name JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
GND+ Unused input. This pin should be connected to GND. It may also be connected to a legal signal on the board (low, high, or toggling) if that signal is required for a different revision of the design.
GND* Unused I/O pin that drives out.


The following example shows a portion of the All Package Pins section for a sample design:


All Package Pins Section (Compilation Report)


The following example shows a portion of the All Package Pins section when you select an ACEX® 1K, FLEX 10KE, or MAX® 7000 for compilation, select one or more migration devices and turn on Base the Pin-Out File (.pin) and floorplan package views on the largest selected SameFrame™ device in the Migration Devices dialog box, which is available from the Device page of the Settings dialog box (Assignments menu).


All Package Pins Section (Compilation Report)


NOTE

  1. Pin and other resource assignments made by the Fitter may change if you change the design file(s). To retain the current assignments for future use, you must back-annotate them to the original design files for the project.

  2. The Quartus® II software automatically generates a Pin-Out File (.pin), which is a text file that lists pin-out information. This file can be used with other EDA tools.

For information on the resources available in a particular device, refer to the individual device data sheets, which are available from the Literature section of the Altera® web site, or to Devices & Adapters. The data sheet information helps you choose resource assignments that enable the Fitter to find a satisfactory fit for the project.


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