See Also

The CLKLOCK primitive enables phase-locked loop, or ClockLock^®, circuitry. The CLKLOCK primitive can reduce clock delay and skew and can be used to generate internal clocks that operate at frequencies equal to or twice the frequency of the system clock. The CLKLOCK primitive can also improve t_su and t_h. Once CLKLOCK is locked onto the clock, it generates a clock signal that appears to have a negative delay with respect to the incoming clock. The negative delay is designed to approximate the delay from CLKLOCK to the register, therefore minimizing the apparent delay from the clock pin to the register. Altera^® recommends using the altclklock megafunction rather than the CLKLOCK primitive.

The CLKLOCK primitive is available only for backwards compatibility with the MAX+PLUS^® II clklock megafunction. The Quartus^® II software automatically replaces the CLKLOCK primitive with an equivalent instantiation of the altclklock megafunction.