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To create a VHDL Design File (.vhd) or a Verilog Design File (.v) for the current Block Design File (.bdf):

1. Open a new or existing project.

2. Create a new BDF or open an existing one for the project.

3. Choose Create/Update > Create HDL Design File for Current File (File menu).

4. Select the type of HDL design file you want to create.  More Details

5. If you select VHDL, to add VHDL statements:

   1. To open the VHDL Statements tab (File Properties dialog box), click Add VHDL Statements.

   2. In the VHDL Statements box, type the VHDL statements.

   3. Click OK.

6. Click OK.

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