Specifies routing paths between the embedded processor core and programmable logic device (PLD) of an EPXA4 or EPXA10 device using the following options:
| Stripe-To-PLD Bridge |
Routes the Stripe-To-PLD Bridge to MegaLAB™ column 1 or 2. When the Stripe-To-PLD Bridge is routed to a MegaLAB column, the PLD-To-Stripe Bridge is automatically routed to the other MegaLAB column. For example, when the Stripe-To-PLD Bridge is routed to MegaLAB column 1, the PLD-to-Stripe Bridge is automatically routed to MegaLAB column 2. |
| Stripe-To-PLD Interrupts |
Routes the Stripe-To-PLD Interrupts to MegaLAB column 1 or 2. In EPXA4 devices, the Stripe-To-PLD Interrupts from UART and TIMER0 are always routed to the same MegaLAB column as the PLD-To-Stripe Bridge. |
| PLD-To-Stripe Interrupts |
Routes the PLD-To-Stripe Interrupts to MegaLAB column 1 or 2. |
| Processor debug extensions |
Routes the embedded processor core debug extensions to MegaLAB column 1 or 2. In EPXA10 devices, the three MSB bits of the trace port debug inputs from the PLD are always routed to the same MegaLAB column as the PLD-To-Stripe Bridge. In EPXA4 devices, the three LSB bits of the trace port debug inputs from the PLD, the debug request signal, and two debug inputs from the PLD are always routed to the same MegaLAB column as the Stripe-To-PLD Bridge. |
