See Also

The Quartus^® II software sends the following information to the HardCopy^™ HC20K Power Calculator page on the Altera^® web site:

• The target device for the current design.

• The package for the target device.

• The temperature grade of the target device.

• The f_MAX of each of the design's clock domains.

• The number of flipflops in each clock domain.

• The number of logic elements in each clock domain.

• The number of output and bidirectional pins in each clock domain.

• The number of Embedded System Blocks (ESBs) in each clock domain.

You do not have to manually enter this information in the HardCopy HC20K Power Calculator page when you open the page from the Quartus II software. However, you must manually enter all other relevant information in the HardCopy HC20K Power Calculator page, including the following information:

• TOG_IO, which is the average percentage of logic cells toggling at each clock domain (this value defaults to 12.5%).

• The average capacitive load for each output pin (this value defaults to 10pF).

• PDCout, which is the DC output power of the output buffers.

• T_A, which is the ambient temperature of the design.

After you finish entering information in the HardCopy HC20K Power Calculator page, click Calculate to direct the HardCopy HC20K Power Calculator to estimate power requirements for the current design.

A design must be successfully compiled before the Quartus II software can open the HardCopy HC20K Power Calculator page for the design. If you successfully compile a design, change any timing requirements for the design, and then want to open the HardCopy HC20K Power Calculator page, you must first run a timing analysis on the design.