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The Compiler generates logic for a state machine using the state machine design you specify in a Text Design File (.tdf). If you specify a state machine design that explicitly declares state bits and also does not use one-hot encoding, the Compiler can generate logic where state bit values are not assigned to valid states. These unassigned or incorrectly assigned state bit values are called illegal states. A state machine that enters an illegal state—for example, as a result of setup time (t_SU) or hold time (t_H) violations—can produce erroneous outputs.You can make a state machine recover from an illegal state in one of the following ways:

Although a state machine can recover from an illegal state it enters due to a tSU or tH violation, Altera® recommends that state machine inputs meet all tSU and tH requirements.

• Set the State Machine Processing logic option to One-Hot, which implements one-hot encoding for a project. One-hot encoding automatically assigns all state bits to valid states. However, if you explicitly assign state bits in addition to using one-hot encoding, the project's logic may be implemented inefficiently.

• Force any illegal states in the state machine to known states using the WHEN OTHERS clause in the state machine's Case Statement. To use the WHEN OTHERS clause, you must declare all illegal states (with dummy names) in the state machine's State Machine Declaration, and you must not use the illegal state in a WHEN clause of the state machine's Case Statement.

  For an n-bit state machine, 2^n possible states exist. If you declare n bits in a state machine, you should continue to add dummy states to the state machine's State Machine Declaration until the number of states reaches a power of 2. The recover.tdf file shown below contains a state machine that can recover from illegal states.

  SUBDESIGN recover 
  (
     clk : INPUT;
     go  : INPUT; 
     ok  : OUTPUT;
  )
  VARIABLE
     sequence : MACHINE 
              OF BITS (q[2..0])
              WITH STATES (   
                 idle, 
                 one, 
                 two, 
                 three, 
                 four, 
                 illegal1,    
                 illegal2,    
                 illegal3);
  BEGIN
     sequence.clk = clk;
  
     CASE sequence IS
        WHEN idle =>
           IF go THEN
              sequence = one;
           END IF;
        WHEN one =>
           sequence = two;
        WHEN two =>
           sequence = three;
        WHEN three =>
           sequence = four;
        WHEN OTHERS =>
           sequence = idle;
     END CASE;
  
     ok = (sequence == four);
  END;
  

  This example contains 3 bits: q2, q1, and q0. Therefore, 2^3 states, or 8 states, exist. Because this example contains only 5 declared states, it also contains 3 dummy states, creating a total of 8 states.

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