See Also

Enables the lock output, which is available in devices with ClockLock^® phase-locked loop (PLL) circuitry. The lock output monitors when the digital phase detector locks the input signal. The Enable LOCK output option is provided primarily for backward compatibility with MAX+PLUS^® II designs. Altera^® recommends using the MegaWizard^® Plug-In Manager to instantiate PLLs and to enable the LOCK output in new designs. This option is ignored if it is assigned to a device that does not have the PLL feature.