Simulating SEU Events in Actel EDAC RAMs

Actel's designed-for-space RTAX-S low-power FPGAs provide embedded user static RAM in addition to single-event-upset (SEU)-enhanced logic.

The SEU-enhanced logic consists of triple-module-redundant (TMR) registers embedded in the silicon. However, the embedded user SRAM does not include any embedded mitigation capabilities. The integrity requirement of the data contained within the embedded SRAM is determined by the particular application and may range from non-critical, such as the pixel data for an image, to very critical, such as a header for a communication packet or a data word for a control application. Designers must determine whether the EDAC core is required in their application. If so, they must determine the configuration of the EDAC core, as well as how the remainder of the design should respond to the notification of an SEU event.

Implementing the SRAM blocks in conjunction with the Actel EDAC core can significantly improve the SEU performance of these embedded SRAM blocks for critical data applications. While the Actel EDAC core provides mitigation and/or notification of SEU-induced errors within the embedded SRAM memories, verifying the user control logic associated with an SEU-induced error is challenging because the user must induce an error that simulates a cosmic event.

Actel uses the functions of the ModelSim® AE simulator, included in the Actel Libero IDE tool suite, to quickly and easily accomplish this verification by mimicking one or more SEU events in the SRAM. One of the capabilities included in the ModelSim simulator is the ability to force a value onto a node within the design, until a new event triggers a new value to be driven onto that same node. The Simulating SEU Events in EDAC RAM application note describes how to use this ModelSim feature.

Test configuration options are dependent on the configuration of the EDAC core. In each case, certain levels of simulation are possible as described below:

EDAC memories with no Error Flags or Test Ports

SEU events can be simulated, but observability is limited to verifying that the read data in the simulation is correct for one "induced SEU" event and is incorrect for two "induced SEU" events.

EDAC memories with Error Flags

SEU events can be simulated. In addition to observing the correct data for one "induced SEU event," the Corrected signal will indicate that the EDAC core found and corrected an error in the SRAM data. In the case of two "induced SEU events", not only will the read data be incorrect but the Error signal will also indicate that the EDAC core found an uncorrectable error.

EDAC memories with Error Flags and Test Ports

SEU events can be simulated and observed at the data word, Error signal, or Corrected signal. Additionally, the Test ports are available if the user wants to add simulation vectors to manipulate the parity bits of the coded word.

Functional Diagram of EDAC RAM