ÀÌ ¹®¼¿¡´Â CPU ¼³°è¿Í Á¦Á¶¿¡ °üÇÑ ¹æ´ëÇÑ URL ¸®½ºÆ®µéÀÌ Æ÷ÇԵǾî ÀÖ´Ù. ¿©·¯ »ç¶÷µéÀÌ Linux³ª Unix ¿î¿µÃ¼Á¦¸¦ ±¸µ¿ÇÒ ¼ö ÀÖ´Â »õ·Î¿î CPU¸¦ ¸¸µå´Âµ¥ ÁÁÀº Âü°íÀÚ·á°¡ µÉ °ÍÀ̶ó°í »ý°¢ÇÑ´Ù.
¿¹Àü¿¡´Â, Ĩ Á¦Á¶È¸»çµéÀÌ IP °³¹ßÀÚÀÌÀÌ¸é¼ EDA tool °³¹ßÀÚ ¿ªÇÒ±îÁö ÇÏ¿´´Ù. ÇÏÁö¸¸, ÃÖ±Ù¿¡ µé¾î, ¿ì¸®´Â Àü¹®ÈµÈ ȸ»çµé (TSMC http://www.tsmc.com), IP Àü¹® ȸ»çµé (ARM http://www.arm.com, MIPS http://www.mips.com, Gray Research LLC http://cnets.sourceforge.net/grllc.html ), tool Àü¹® °³¹ß»çµé ( Mentor http://www.mentor.com, Cadence http://www.cadence.com, etc.), ±×¸®°í À̵éÀ» ¸ðµÎ °¡Áö°í Àִ ȸ»ç(Intel)¸¦ ¹ß°ßÇÒ ¼ö ÀÖ´Ù. ¿©·¯ºÐÀº IP¸¦ Çϵå¿þ¾î¿¡ Æ÷ÇÔµÈ ÇüÅ·Π»ì ¼öµµ ÀÖ°í (Intel), Åø°ú °°ÀÌ »ì ¼öµµ ÀÖ°í (EDA companies), IP ¸¸À» °³º°ÀûÀ¸·Î ±¸ÀÔÇÒ ¼öµµ ÀÖ´Ù (IP providers).
FPGA [1] Á¦Á¶ ȸ»çµé ȨÆäÀÌÁö (Xilinx http://www.xilinx.com, Altera [2] http://www.altera.com). ÀÌ »çÀÌÆ®µéÀ» ¹æ¹®Çغ¸´Â °ÍÀº µ¶Æ¯ÇÑ »ç¾÷ ¸ðµ¨À» Æ÷ÂøÇÒ ¼ö ÀÖ´Â ÁÁÀº ±âȸ°¡ µÉ °ÍÀÌ´Ù.
VA Linux systems http://www.valinux.com Àº ½Ã½ºÅÛ Àüü¸¦ ±¸ÃàÇÏ°í ÀÖÀ¸¸ç, °¡±î¿î ½ÃÀϳ»¿¡ Linux ¿ëÀÇ CPU¸¦ ¼³°èÇÏ°í Á¦Á¶ÇÒ ¼ö ÀÖÀ» °ÍÀ¸·Î º¸ÀδÙ.
¾Æ·¡ÀÇ CPU ¼³°è »çÀÌÆ®µéÀ» ¹æ¹®ÇØ º¸¶ó:
FPGA CPU ¸µÅ©µé http://www.fpgacpu.org/links.html
FPGA ¸ÞÀÎ »çÀÌÆ® http://www.fpgacpu.org
OpenRISC 1000 (½ÃÀåÀ» µ¶Á¡ÇÏ°í ÀÖ´Â ARM°ú MIPS¿Í °æÀïÁßÀÎ °øÂ¥ ¿ÀÇ ¼Ò½º 32-bit RISC [3] processor) IP core http://www.opencores.org
¿ÀÇ IP ´Üü http://www.openip.org
Free IP ´Üü - ´ëÁßÀ» À§ÇÑ ASIC°ú FPGA coreµé http://www.free-ip.com
[1] | Field Programmable Gate Array, Xilinx¿¡¼ ¸¸µå´Â ÇÁ·Î±×·¥ °¡´ÉÇÑ ³í¸®È¸·Î |
[2] | MAX, FLEX seriesµîÀÇ PLD(Programmable Logic Device)¸¦ ¸¸µå´Â ȸ»ç |
[3] | Reduced Instruction Set Computing. Instruction ¼ö¸¦ ÁÙÀÌ°í registerÀÇ ¼ö¸¦ ´Ã¸° CPU design ¹æ½Ä |
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