VHDL: Introduction

I've never been very good with a soldering iron but at the same time I've always wanted to understand electronics better, especially digital electronics . Early in 2004 I was surfing around cyberspace when I came across the home pages of someone who had built a Motorola 6809 based system running Flex using a Field Programmable Gate Array (FPGA). I was intrigued and decided to learn more about these devices and how you program them to simulate microprocessors.

Since March 2004 I've been playing with VHDL. My initial experiments were too ambitious and recently I decided to go back to basics and simulate some simple logic components before attempting more complex devices (like the Intel 4004, MOS 6502, WDC 65C02 and 65816).

In January 2005 I finally bought a XESS XSA-3M1000 development board with 1,000,000 gate Spartan-3 FPGA but I'm still working on the VHDL model for my CPU.

There is a lot of information about VHDL on the Internet but surprisingly few examples of simple designs for beginners so I've been downloading data sheets for CMOS and 74 Series logic chips and working out how to code them. I use two development environments to check my models, the Xilinx ISE 6.3 (a free download but you need cable/DSL as it's huge) with ModelSim XE and Green Mountain DirectVHDL 1.1.2 (reasonably priced for a beginner).

I'm a professional software engineer by training and not an electronics engineer so it has taken me a while to get my head around differences between '0' and 'L' and propagation delays. If you have any comments on my models then drop me an e-mail (removing the SPAM protection) and tell me what I've done wrong or how to improve them.

In writing my models I've adopted a number of conventions, namely:

I write my VHDL in 'lower case' with 4 space tabs. If you don't like this then tough!
I indicate active low signals by suffixing them with '_n' (as in 'clk_n').
I try to make my models work with '0', '1', 'L' and 'H' inputs. Outputs are normally '0' or '1'.
My components uses generic constants to define 'High-to-Low' and 'Low-to-High' propagation times. In the models these time constants are zero but you can substitute real values when you create instances of them as components (see the test benches for examples).
Lots of device names are not valid VHDL identifiers. I add an 'A' prefix to my model names (e.g. 4001B => A4001B).
Some devices names include codes to indicate the technology they are manufactured with (e.g. 74LSxxx and 74HCxxx). This typically does not affect the function only its speed which in my models is determined at instantiation, so I put 'XX' in the device name (e.g. 74LS138 => A74XX138).

I only upload design files that compile and produce reasonable looking schematics, but if it doesn't have a test bench then its behaviour has not been fully tested. I'll be adding more designs and test benches over time so check back occasionally to see what's changed.

A word to students:

I don't mind you looking at my code to see how I wrote it but I wouldn't advise copying it verbatim and trying to pass it off as your own. If you found this page then your lecturer probably has too! Have an attempt at working out how to code a problem yourself first then compare it to mine.

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This page was last updated on 21st April 2009