Variables

VHDL Objects

Variables

Variables are used for local storage of data
Variables are generally not available to multiple components and processes

All variable assignments take place immediately

   VARIABLE variable_name : type_name [:=value];

   VARIABLE opcode : BIT_VECTOR (3 DOWNTO 0) := "0000";
   VARIABLE freq : INTEGER;

Variables are more convenient than signals for the storage of data
Variables may be made global