Two State Processes
REG: process (CLK, RESET)
begin
if RESET=`1` then STATE <= START ;
elsif CLK`event and CLK=`1` then
STATE <= NEXTSTATE ;
end if ;
end process REG;
CMB: process (A,B,STATE)
begin
NEXTSTATE <= STATE ;
case STATE is
when START => if (A or B)=`0` then
NEXTSTATE <= MIDDLE ;
end if ;
when MIDDLE => if (A and B)=`1` then
NEXTSTATE <= STOP ;
end if ;
when STOP => if (A xor B)=`1` then
NEXTSTATE <= START ;
end if ;
when others => NEXTSTATE <= START ;
end case ;
end process CMB ;
Y <= ... ;
Z <= ... ;
|
One State Process
REG: process (CLK, RESET)
begin
if RESET=`1` then
STATE <= START ;
elsif CLK`event and CLK=`1` then
case STATE is
when START => if (A or B)=`0` then
STATE <= MIDDLE ;
end if ;
when MIDDLE => if (A and B)=`1` then
STATE <= STOP ;
end if ;
when STOP => if (A xor B)=`1` then
STATE <= START ;
end if ;
when others => STATE <= START ;
end case ;
end if ;
end process REG ;
Y <= ... ;
Z <= ... ;
|