Registered Output Example (2)

architecture RTL of REG_TEST2 is
    signal Y_I,Z_I : std_ulogic ;
    signal STATE,NEXTSTATE : STATE_TYPE ;
begin
    REG: process (CLK, RESET) begin
       -- Like before
       end if ;
    end process REG;
    CMB: process (A,B,STATE) begin
       -- Like before
    end process CMB ;
    -- concurrent signal assignments for output
    Y_I <= `1` when (NEXTSTATE=MIDDLE and (A or B)=`0`)
                 or (NEXTSTATE=STOP and (A and B)=`0`)
               else `0` ;
    Z_I <= `1` when (NEXTSTATE=START and (A and B)=`1`)
                 or (NEXTSTATE=MIDDLE)
                 or (NEXTSTATE=STOP and (A or B)=`1`)
               else `0` ;
    OUTPUT: process(CLK)
    begin
       if CLK'event and CLK='1' then
          Y <= Y_I ;
          Z <= Z_I ;
       end if ;
    end process OUTPUT ;
end RTL ;