mti_AddRestartCB()

Adds a simulator restart callback.

Syntax

mti_AddRestartCB( func, param ) 

Returns

Nothing

Arguments

Name	Type	Description
func	mtiVoidFuncPtrT	A pointer to a function to be called when the simulator restarts
param	void *	A parameter to be passed to the function; OPTIONAL - can be NULL

Description

mti_AddRestartCB() adds the specified function to the simulator restart callback list. The same function can be added multiple times, with possibly a different parameter each time. When the simulator restarts, all callbacks in the list are called with their respective parameters before the simulator is restarted. The callback function should do a cleanup operation including freeing any allocated memory and resetting global/static variables.

When the "quit -sim" command is given to vsim, restart callbacks are called because the simulator is not completely quitting but may be restarting the previous design or loading a new design.

Related functions

mti_RemoveRestartCB()

Example

FLI code

#include <stdlib.h>
#include <mti.h>

void restartCallback( void * param )
{
  mti_PrintFormatted( "Cleaning up %s for simulator restart ...\n",
                     (char *)param );
  free( param );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  char * instance_info;

  instance_info = malloc( strlen(param) + 1 );
  strcpy( instance_info, param );
  mti_AddRestartCB( restartCallback, instance_info );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is
   "initForeign for_model.sl; for_model";
begin
end a;

entity top is
end top;

architecture a of top is

  signal s1 : bit := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

begin

  i1 : for_model;

  s1 <= not s1 after 5 ns;

end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
VSIM 1> run 10
VSIM 2> restart -f
# Cleaning up for_model for simulator restart ...
# Loading ./for_model.sl
VSIM 3> quit 

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