mti_GetDrivingSignals()

Gets a handle to all of the signals driving a signal.

Syntax

signal_list = mti_GetDrivingSignals( signal_name ) 

Returns

Name	Type	Description
signal_list	mtiSignalIdT *	A NULL-terminated array of driving signal IDs for the specified signal or NULL if there is an error or no drivers are found

Arguments

Name	Type	Description
signal_name	char *	The name of the signal for which the driving signals are to be found

Description

mti_GetDrivingSignals() returns a NULL-terminated array of driving signal IDs for the specified signal. The signal is specified by name using either a full hierarchical name or a relative name. A relative name is relative to the region set by the environment command. The default is the top-level region.

The caller is responsible for freeing the returned pointer with mti_VsimFree().

mti_GetDrivingSignals() returns the same signal IDs as those used by the drivers command to generate the signal part of its output.

Related functions

mti_GetDriverNames()

mti_GetDriverValues()

Example

FLI code

#include <stdlib.h>
#include <mti.h>

typedef enum {
  STD_LOGIC_U,
  STD_LOGIC_X,
  STD_LOGIC_0,
  STD_LOGIC_1,
  STD_LOGIC_Z,
  STD_LOGIC_W,
  STD_LOGIC_L,
  STD_LOGIC_H,
  STD_LOGIC_D
} standardLogicType;

typedef struct {
  char *        signame;
  mtiSignalIdT  sigid;
  mtiProcessIdT procid;
} instanceInfoT;

char * convertStdLogicValue( mtiInt32T sigval )
{
  char * retval;

  switch ( sigval ) {
    case STD_LOGIC_U:  retval = "'U'";  break;
    case STD_LOGIC_X:  retval = "'X'";  break;
    case STD_LOGIC_0:  retval = "'0'";  break;
    case STD_LOGIC_1:  retval = "'1'";  break;
    case STD_LOGIC_Z:  retval = "'Z'";  break;
    case STD_LOGIC_W:  retval = "'W'";  break;
    case STD_LOGIC_L:  retval = "'L'";  break;
    case STD_LOGIC_H:  retval = "'H'";  break;
    case STD_LOGIC_D:  retval = "'-'";  break;
    default:  retval = "?";  break;
  }
  return retval;
}

void checkSignal( void * param )
{
  char          * region_name;
  instanceInfoT * inst = (instanceInfoT*)param;
  int             i;
  mtiInt32T       sigval;
  mtiSignalIdT  * drv_signals;

  sigval = mti_GetSignalValue( inst->sigid );
  mti_PrintFormatted( "Time [%d,%d] delta %d:\n Signal %s is %s\n",
                     mti_NowUpper(), mti_Now(), mti_Delta(),
                     inst->signame, convertStdLogicValue( sigval ) );

  mti_PrintFormatted( " Driving Signals for %s:\n", inst->signame );
  drv_signals = mti_GetDrivingSignals( inst->signame );
  for ( i = 0; drv_signals[i]; i++ ) {
   region_name =
     mti_GetRegionFullName( mti_GetSignalRegion( drv_signals[i] ));
   mti_PrintFormatted( "     %s/%s\n", region_name,
                      mti_GetSignalName( drv_signals[i] ) );
   mti_VsimFree( region_name );
  }
  mti_ScheduleWakeup( inst->procid, 5 );
}

void cleanupCallback( void * param )
{
  mti_PrintMessage( "Cleaning up...\n" );
  free( param );
}
void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  instanceInfoT * inst;

  inst            = (instanceInfoT *)malloc( sizeof(instanceInfoT) );
  inst->signame   = "/top/s1";
  inst->sigid     = mti_FindSignal( inst->signame );
  inst->procid    = mti_CreateProcess( "checkSignal", checkSignal, inst );
  mti_ScheduleWakeup( inst->procid, 1 );
  mti_AddQuitCB( cleanupCallback, inst );
  mti_AddRestartCB( cleanupCallback, inst );
} 

HDL code

library ieee;
use ieee.std_logic_1164.all;

entity lower is
  port ( pt1 : OUT std_logic := '0';
         pt2 : IN  std_logic
       );
end lower;

architecture a of lower is
begin

  pt1 <= pt2 after 5 ns;

end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is
end top;

architecture a of top is

  signal s1 : std_logic := '0';
  signal s2 : std_logic := '0';

  component lower
    port ( pt1 : OUT std_logic;
           pt2 : IN  std_logic
         );
  end component;

begin

  s2 <= not s2 after 5 ns;

  s1 <= s2 after 5 ns;

  p1 : process
    begin
      s1 <= 'H';
      wait for 5 ns;
      s1 <= 'L';
      wait for 5 ns;
      s1 <= 'W';
      wait for 5 ns;
    end process;

  inst1 : lower port map ( s1, s2 );

end a; 

Simulation output

% vsim -c top -foreign "initForeign for_model.sl"
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -foreign {initForeign for_model.sl} -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.lower(a)
# Loading ./for_model.sl
VSIM 1> run 1
# Time [0,1] delta 0:
#  Signal /top/s1 is '0'
#  Driving Signals for /top/s1:
#      /top/s1
VSIM 2> drivers /top/s1
# Drivers for /top/s1:
#  0 : Signal /top/s1
#    0 : Driver /top/inst1/line__14
#    H : Driver /top/p1
#    0 : Driver /top/line__39
# 
VSIM 3> run 5
# Time [0,6] delta 0:
#  Signal /top/s1 is '0'
#  Driving Signals for /top/s1:
#      /top/s1
VSIM 4> drivers /top/s1
# Drivers for /top/s1:
#  0 : Signal /top/s1
#    0 : Driver /top/inst1/line__14
#        1 at 10 ns
#    L : Driver /top/p1
#    0 : Driver /top/line__39
#        1 at 10 ns
# 
VSIM 5> quit
# Cleaning up... 

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