mti_CreateTimeType()

Creates a time type.

Syntax

type_id = mti_CreateTimeType() 

Returns

Name	Type	Description
type_id	mtiTypeIdT	A handle to the new time type

Arguments

None

Description

mti_CreateTimeType() creates a new type ID that describes a VHDL time type.

Related functions

mti_CreateArrayType()

mti_CreateEnumType()

mti_CreateRealType()

mti_CreateScalarType()

Example

FLI code

#include <stdlib.h>
#include <mti.h>

typedef struct {
    mtiSignalIdT sigid;
    mtiDriverIdT drvid;
    mtiTime64T   sigval;
    mtiTypeIdT   time_type;
} instanceInfoT;

void driveSignal( void * param )
{
    char          * region_name;
    char          * curr_time_str;
    instanceInfoT * inst = (instanceInfoT*)param;
    mtiTime64T      curr_time;

    region_name = mti_GetRegionFullName( mti_GetSignalRegion( inst->sigid ) );

	curr_time_str = mti_Image( mti_NowIndirect(&curr_time), inst->time_type );
    mti_PrintFormatted( "Time %s delta %d: Signal %s/%s is %s\n",
                       curr_time_str, mti_Delta(),
                       region_name, mti_GetSignalName( inst->sigid),
                       mti_SignalImage(inst->sigid) );

    MTI_TIME64_ASGN( inst->sigval, MTI_TIME64_HI32(inst->sigval),
                    MTI_TIME64_LO32(inst->sigval) + 1 );
    mti_ScheduleDriver( inst->drvid, (long)&(inst->sigval), 5, MTI_INERTIAL );

    mti_VsimFree( region_name );
}

void initForeign(
    mtiRegionIdT       region,   /* The ID of the region in which this       */
                                 /* foreign architecture is instantiated.    */
    char              *param,    /* The last part of the string in the       */
                                 /* foreign attribute.                       */
    mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
    mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
    instanceInfoT * inst;
    mtiProcessIdT   procid;

    inst            = (instanceInfoT *)mti_Malloc( sizeof(instanceInfoT) );
    inst->time_type = mti_CreateTimeType();
    inst->sigid     = mti_CreateSignal( "mySig", region, inst->time_type );
    inst->drvid     = mti_CreateDriver( inst->sigid );
    procid          = mti_CreateProcess( "mySigDriver", driveSignal, inst );
    mti_SetDriverOwner( inst->drvid, procid );
    mti_Sensitize( procid, inst->sigid, MTI_EVENT );
    mti_ScheduleWakeup( procid, 0 );
} 

HDL code

entity top is
end top;

architecture a of top is

  signal s1 : bit := '0';

begin

  s1 <= not s1 after 5 ns;

end a; 

Simulation output

% vsim -c top -foreign "initForeign for_model.sl"
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl

# 5.5b

# vsim -foreign {initForeign for_model.sl} -c top
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading ./for_model.sl
VSIM 1> run 50
# Time 0 ns delta 1: Signal /top/mysig is 0 ns
# Time 5 ns delta 0: Signal /top/mysig is 1 ns
# Time 10 ns delta 0: Signal /top/mysig is 2 ns
# Time 15 ns delta 0: Signal /top/mysig is 3 ns
# Time 20 ns delta 0: Signal /top/mysig is 4 ns
# Time 25 ns delta 0: Signal /top/mysig is 5 ns
# Time 30 ns delta 0: Signal /top/mysig is 6 ns
# Time 35 ns delta 0: Signal /top/mysig is 7 ns
# Time 40 ns delta 0: Signal /top/mysig is 8 ns
# Time 45 ns delta 0: Signal /top/mysig is 9 ns
# Time 50 ns delta 0: Signal /top/mysig is 10 ns
VSIM 2> quit 

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