mti_NowUpper()

Gets the high order 32 bits of the 64-bit current simulation time.

Syntax

high_time = mti_NowUpper() 

Returns

Name	Type	Description
high_time	mtiInt32T	The high order 32 bits of the current simulation time

Arguments

None

Description

mti_NowUpper() returns the high order 32 bits of the current simulation time. The time units are equivalent to the current simulator time unit setting.

Related functions

mti_Delta()

mti_GetResolutionLimit()

mti_Now()

mti_NowIndirect()

Example

FLI code

#include <mti.h>

typedef struct signalInfoT_tag {
  struct signalInfoT_tag * next;
  char                   * name;
  mtiSignalIdT             sigid;
  mtiTypeIdT               typeid;
} signalInfoT;

typedef struct {
  signalInfoT   * sig_info;     /* List of signals. */
  mtiProcessIdT   proc;         /* Test process id.*/
} instanceInfoT;

static void checkValues( void *inst_info )
{
  instanceInfoT * inst_data = (instanceInfoT *)inst_info;
  signalInfoT   * siginfo;

  mti_PrintFormatted( "Time [%d,%u]:\n", mti_NowUpper(), mti_Now() );

  for ( siginfo = inst_data->sig_info; siginfo; siginfo = siginfo->next ) {
    mti_PrintFormatted( "  Signal %s: %s\n",
                       siginfo->name, mti_SignalImage( siginfo->sigid ));
  }

  mti_ScheduleWakeup( inst_data->proc, 500000000 );
}

static signalInfoT * setupSignal( mtiSignalIdT sigid )
{
  signalInfoT * siginfo;

  siginfo          = (signalInfoT *) mti_Malloc( sizeof(signalInfoT) );
  siginfo->sigid   = sigid;
  siginfo->name    = mti_GetSignalNameIndirect( sigid, 0, 0 );
  siginfo->typeid  = mti_GetSignalType( sigid );
  siginfo->next    = 0;

  return( siginfo );
}

static void initInstance( void )
{
  instanceInfoT * inst_data;
  mtiSignalIdT    sigid;
  signalInfoT   * curr_info;
  signalInfoT   * siginfo;

  inst_data           = mti_Malloc( sizeof(instanceInfoT) );
  inst_data->sig_info = 0;

  for ( sigid = mti_FirstSignal( mti_GetTopRegion() );
        sigid; sigid = mti_NextSignal() ) {
    siginfo = setupSignal( sigid );
    if ( inst_data->sig_info == 0 ) {
      inst_data->sig_info = siginfo;
    }
    else {
      curr_info->next = siginfo;
    }
    curr_info = siginfo;
  }

  inst_data->proc = mti_CreateProcess( "Test Process", checkValues,
                                      (void *)inst_data );
  mti_ScheduleWakeup( inst_data->proc, 600000000 );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( initInstance, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl;";
begin
end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is
end top;

architecture a of top is

  signal intsig      : integer   := 42;
  signal realsig     : real      := 10.2;

  component for_model
  end component;

  for all : for_model use entity work.for_model(a);

begin

  inst1 : for_model;

  intsig      <= intsig + 1 after 5000000 sec;
  realsig     <= realsig + 1.1 after 5000000 sec;

end a; 

Simulation output

% vsim -c top -t sec
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -t sec -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
VSIM 1> run 10000000000
# Time [0,600000000]:
#   Signal intsig: 162
#   Signal realsig: 142.2
# Time [0,1100000000]:
#   Signal intsig: 262
#   Signal realsig: 252.2
# Time [0,1600000000]:
#   Signal intsig: 362
#   Signal realsig: 362.2
# Time [0,2100000000]:
#   Signal intsig: 462
#   Signal realsig: 472.2
# Time [0,2600000000]:
#   Signal intsig: 562
#   Signal realsig: 582.2
# Time [0,3100000000]:
#   Signal intsig: 662
#   Signal realsig: 692.2
# Time [0,3600000000]:
#   Signal intsig: 762
#   Signal realsig: 802.2
# Time [0,4100000000]:
#   Signal intsig: 862
#   Signal realsig: 912.2
# Time [1,305032704]:
#   Signal intsig: 962
#   Signal realsig: 1022.2
# Time [1,805032704]:
#   Signal intsig: 1062
#   Signal realsig: 1132.2
# Time [1,1305032704]:
#   Signal intsig: 1162
#   Signal realsig: 1242.2
# Time [1,1805032704]:
#   Signal intsig: 1262
#   Signal realsig: 1352.2
# Time [1,2305032704]:
#   Signal intsig: 1362
#   Signal realsig: 1462.2
# Time [1,2805032704]:
#   Signal intsig: 1462
#   Signal realsig: 1572.2
# Time [1,3305032704]:
#   Signal intsig: 1562
#   Signal realsig: 1682.2
# Time [1,3805032704]:
#   Signal intsig: 1662
#   Signal realsig: 1792.2
# Time [2,10065408]:
#   Signal intsig: 1762
#   Signal realsig: 1902.2
# Time [2,510065408]:
#   Signal intsig: 1862
#   Signal realsig: 2012.2
# Time [2,1010065408]:
#   Signal intsig: 1962
#   Signal realsig: 2122.2
VSIM 2> quit 

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