![]() |
![]() |
![]() |
![]() |
mti_Now()
Gets the low order 32 bits of the 64-bit current simulation time.
Syntax
low_time = mti_Now()Returns
Name Type Description low_time mtiInt32T The low order 32 bits of the current simulation timeArguments
Description
mti_Now() returns the low order 32 bits of the current simulation time. The time units are equivalent to the current simulator time unit setting.
Related functions
Example
FLI code
#include <mti.h> typedef struct signalInfoT_tag { struct signalInfoT_tag * next; char * name; mtiSignalIdT sigid; mtiTypeIdT typeid; } signalInfoT; typedef struct { signalInfoT * sig_info; /* List of signals. */ mtiProcessIdT proc; /* Test process id.*/ } instanceInfoT; static char * convertTime( mtiInt32T time, int limit, mtiInt32T * new_time ) { switch ( limit ) { case 2: *new_time = time * 100; return( "sec" ); case 1: *new_time = time * 10; return( "sec" ); case 0: *new_time = time; return( "sec" ); case -1: *new_time = time * 100; return( "ms" ); case -2: *new_time = time * 10; return( "ms" ); case -3: *new_time = time; return( "ms" ); case -4: *new_time = time * 100; return( "us" ); case -5: *new_time = time * 10; return( "us" ); case -6: *new_time = time; return( "us" ); case -7: *new_time = time * 100; return( "ns" ); case -8: *new_time = time * 10; return( "ns" ); case -9: *new_time = time; return( "ns" ); case -10: *new_time = time * 100; return( "ps" ); case -11: *new_time = time * 10; return( "ps" ); case -12: *new_time = time; return( "ps" ); case -13: *new_time = time * 100; return( "fs" ); case -14: *new_time = time * 10; return( "fs" ); case -15: *new_time = time; return( "fs" ); default: *new_time = time; return( "??" ); } } static void checkValues( void *inst_info ) { char * units; instanceInfoT * inst_data = (instanceInfoT *)inst_info; mtiInt32T new_time; signalInfoT * siginfo; units = convertTime( mti_Now(), mti_GetResolutionLimit(), &new_time ); mti_PrintFormatted( "Time %d %s:\n", new_time, units ); for ( siginfo = inst_data->sig_info; siginfo; siginfo = siginfo->next ) { mti_PrintFormatted( " Signal %s: %s\n", siginfo->name, mti_SignalImage( siginfo->sigid )); } mti_ScheduleWakeup( inst_data->proc, 5 ); } static signalInfoT * setupSignal( mtiSignalIdT sigid ) { signalInfoT * siginfo; siginfo = (signalInfoT *) mti_Malloc( sizeof(signalInfoT) ); siginfo->sigid = sigid; siginfo->name = mti_GetSignalNameIndirect( sigid, 0, 0 ); siginfo->typeid = mti_GetSignalType( sigid ); siginfo->next = 0; return( siginfo ); } static void initInstance( void ) { instanceInfoT * inst_data; mtiSignalIdT sigid; signalInfoT * curr_info; signalInfoT * siginfo; inst_data = mti_Malloc( sizeof(instanceInfoT) ); inst_data->sig_info = 0; for ( sigid = mti_FirstSignal( mti_GetTopRegion() ); sigid; sigid = mti_NextSignal() ) { siginfo = setupSignal( sigid ); if ( inst_data->sig_info == 0 ) { inst_data->sig_info = siginfo; } else { curr_info->next = siginfo; } curr_info = siginfo; } inst_data->proc = mti_CreateProcess( "Test Process", checkValues, (void *)inst_data ); mti_ScheduleWakeup( inst_data->proc, 6 ); } void initForeign( mtiRegionIdT region, /* The ID of the region in which this */ /* foreign architecture is instantiated. */ char *param, /* The last part of the string in the */ /* foreign attribute. */ mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/ mtiInterfaceListT *ports /* A list of ports for the foreign model. */ ) { mti_AddLoadDoneCB( initInstance, 0 ); }HDL code
entity for_model is end for_model; architecture a of for_model is attribute foreign of a : architecture is "initForeign for_model.sl;"; begin end a; library ieee; use ieee.std_logic_1164.all; entity top is end top; architecture a of top is signal bitsig : bit := '1'; signal intsig : integer := 42; signal realsig : real := 10.2; signal timesig : time := 3 ns; signal stdlogicsig : std_logic := 'H'; signal stdlogicarr : std_logic_vector( 1 to 4 ) := "01LH"; component for_model end component; for all : for_model use entity work.for_model(a); begin inst1 : for_model; bitsig <= not bitsig after 5 ns; intsig <= intsig + 1 after 5 ns; realsig <= realsig + 1.1 after 5 ns; timesig <= timesig + 2 ns after 5 ns; stdlogicsig <= not stdlogicsig after 5 ns; stdlogicarr <= not stdlogicarr after 5 ns; end a;Simulation output
% vsim -c top Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl # 5.4b # vsim -c top # Loading .../modeltech/sunos5/../std.standard # Loading .../modeltech/sunos5/../ieee.std_logic_1164(body) # Loading work.top(a) # Loading work.for_model(a) # Loading ./for_model.sl VSIM 1> run 17 # Time 6 ns: # Signal bitsig: '0' # Signal intsig: 43 # Signal realsig: 11.3 # Signal timesig: 5 ns # Signal stdlogicsig: '0' # Signal stdlogicarr: "1010" # Time 11 ns: # Signal bitsig: '1' # Signal intsig: 44 # Signal realsig: 12.4 # Signal timesig: 7 ns # Signal stdlogicsig: '1' # Signal stdlogicarr: "0101" # Time 16 ns: # Signal bitsig: '0' # Signal intsig: 45 # Signal realsig: 13.5 # Signal timesig: 9 ns # Signal stdlogicsig: '0' # Signal stdlogicarr: "1010" VSIM 2> quit
![]() Model Technology Inc. Voice: (503) 641-1340 Fax: (503)526-5410 http://www.model.com sales@model.com |
![]() |
![]() |
![]() |
![]() |