VHDL Soft Cores

If you want to achieve maximum performance be sure to use a synthesis tool that supports RAM and ROM inferring. Leonardo Spectrum and Synplicity Synplify supports inferring, whereas Synopsys FPGA Express/Compiler do not.

Typical performance for the AX8 and PPX16 cores range from 10 to 100 peek MIPS depending on the FPGA used. The T51 runs at up to about 50 peek MIPS.

I develop these cores on my spare time, this implies that I do not have the time to do a complete verification of them, at least not all of them. So if you want the quality to improve, test them and send me bug reports. Also be aware that only the Z80 core has been tested in hardware, the rest will be tested shortly.

AX8

This core is compatible with 90S1200 and 90S2313.
Except for the watchdog, the analog comparator and the EEPROM all peripherals and interrupts are supported.
There is now a project page at opencores for this core.
Download

PPX16

This core is compatible with 16C55 and 16F84.
The EEPROM is not implemented.
There is now a project page at opencores for this core.
Download

T80

This core is compatible with Z80.
All documented and undocumented instructions and all interrupt modes are implemented. All instructions except the block instructions pass the zex regression test. An assembled NoICE monitor ROM is included in the package and fits with the core and 4k RAM on the BurchED B5 board. It is also possible to configure the core to only support the 8080 instruction set and an incomplete gameboy instruction set.
Currently beta status.
Supports the zxgate ZX81 project.

You need the VHDL utilities to run the testbench and the monitor.
Download

T51

This core is compatible with 8051.

Three stage pipeline. Should be about 10 times as fast as the original 8051 per clock.

WARNING!!!! This core is not yet complete, the MUL, DIV, MOVX instructions are unsupported and the interrupt handling is not complete. Most ports and peripherals are also missing.

You need the VHDL utilities to run the testbench.
Download

Utilities

Some utilities needed to make VHDL ROMs compatible with the above cores and some testbench utilities.

• Hex to VHDL ROM converter that accepts Intel Hex, Motorola S-Record and binary files. Produces ROMs compatible with FPGA ROM inferring.
• An incomplete 16450 UART model.
• Simple SRAM model.
• Inferrable synchronous SRAM model.
• Input port model with binary input from file.
• Output port model with binary output to file.
• Asynchronous serial input port model with binary output to file.
• Asynchronous serial output port model with binary input from file.
• Synchronous serial (I2S) input port model with binary output to file.
• Synchronous serial (I2S) output port model with binary input from file.