Syntax and Example
The keywords used are function at
the head of the required code and endfunction to inform verilog that the
function has been terminated. Function Invocation and Declaration syntax
is given below.
statement = < function name >
( arguments to be passed );
function < range_or_type >
< function name >;
The following example is purely
for providing an idea of how the function is written and implemented within
a Verilog module.
module adder:
reg
[3 : 0] a;
reg
[3 : 0] b;
reg
[4 : 0] sum;
::::::
always@(a
, b ) // a function call must be within an
initial or always
statement
- begin
- sum = ADD( a, b ); //
function invocation with arguments for passing
- :::::::::::::::
end
function [4
: 0] ADD;
// keyword < range_or_type > < function name >
input [3
: 0] first; // argument a is assigned to first
input [3
: 0] second; // argument b is assigned to
second
:::::::::::::
Further Declarations ( Registers,
Integers, Real Numbers, etc.)
begin
// The functions actions has to be performed within a begin statement
- ADD = first + second; //
Action is performed and the result is returned to the point of invocation.
In this case sum = ADD
end
endfunction //
ADD
endmodule //
adder
Some
links to other information within the Verilog Function topic.
Tasks and Functions the Difference
Functions a Description