Most programming languages provide a facility through which lengthy, repetitive, sections of code can be "software engineered" into more manageable routines. Verilog is no different and where common segments of code are used a "function" can be written once and called several times. The functions are normally used to modlle:

The main differences between C and Verilog functions being that in the latter, one must pass one or more arguments to the function when it is invoked. Also the result of the function will return an argument to the point of invocation with a lapse of zero simulation time.

Rules to Follow

A function can only be used if the module has at least one argument to be passed and requires only one argument returned from the function. A function can only be called from within an always or initial block within the module. The function is not allowed to contain either of these two statements, also any delay, event or timing control statements are forbidden. A function can use an input port they are allowed local variables as depicted in the page on syntax. Wires are not allowed and the complete function must be written using behavioral statements only. The actual manipulation of data in the function has to be placed between begin and end statements.