When writing software, some operations, whilst simple in concept and maths require large quantities of code to perform. This operation may be required more than once in a program. Including long procedures in the main of a program, espeicially if repeated, detracts from the flow, readability and de-bugging ease. To this end Verilog supports Tasks and Functions.
Tasks are used in all programming languages, generally known as Procedures or sub routines
(SUBs). Many lines of code are enclosed in
A task is declared with the start and end words task____endtask.
Tasks are local to modules, must be declared outside any begin_end statements of the module, but within the module declarations.
module thermometer; reg [7:0] temperature; begin temperature=100 // initialy assume temperature is in Celcius convert (temperature); // call “convert” passing it the value in C $display(“Temperature is %d F”,temperature); // the register is now in F and displayed end task convert; inout [7:0] temperature; begin temperature=(9/5) * temperature +32; end //begin endtask // task convert endmodule // module thermostat
A task must be specifically called with a statement, it cannot be used within an expression as a function can.
All the processing of a task must be within begin_end calls, including final declarations to outputs. Timing, delay, and event functions may be used within tasks
Tasks may invoke other tasks, themselves or functions.
To call a task the main module uses the name of the task as a complete statement, with variables being in brackets after cf
[Task_name]([variable list]);
The task then copies the variables into its own local variables, performs the action and writes data
directly back into the specified original variables. The above example does not require any further
mention of the variable