Verilog, like any high level language has a number of tokens which we will discuss in this section. Tokens can be comments, delimiters, numbers, strings, identifiers and keywords. All keywords are in lower case.
The white space characters are space (\b), tabs (\t), newlines (\n). These are ignored except in strings
Two types of comments are supported, single line comments starting with
//
and multiple line comments delimited by
/*
...
*/.
Comments cannot be nested.
It is usually a good idea to use single line comments to comment code and multiple lines comments to comment out sections of code when debugging.