Verilog has three types of operators, they take either one, two or three operands. Unary operators appear on the left of their operand, binary in the middle, and ternary seperates its three operands by two operators.
clock = ~clock; // ~ is the unary bitwise negation operator,
// clock is the operand
c = a || b; // || is the binary logical or, a and b are the operands
r = s ? t : u; // ?: is the ternary conditional operator, which
// reads r = [if s is true then t else u]