Large Worked Example

Behavioural Model

In the previous section we saw the gate level description of a binary counter, now we will implement the same counter using a behavioural description. It uses the same stimulus module but is a lot easier to understand and modify.

        // 4-bit binary up-counter - of period 13

        module counter4_bit(q, d, increment, load_data, global_reset, clock);
           output [3:0]     q;
           input [3:0] d;
           input  load_data, global_reset, clock, increment;

           reg [3:0]   q;

           always @(posedge clock)
              if (global_reset)
              q = 4'b0000;
              else if (load_data)
              q = d;
              else if (increment) begin
              if (q == 12)
                 q = 0;
              else
                 q = q + 1;
              end

        endmodule // counter4_bit

EXERCISE Using the stimulus defined in the gate-level description, simulate the behavioural model and verify that the same (correct ?) results are obtained.

This implementation is a lot easier to update than the previous gate level implementation. Circuits are thus normally written in this form and reduced to gate level descriptions by Verilog applications (ie synthesis).

To convert the above into a down counter, all we need to do is changed the + sign in the third if to a - and alter the "end" condition so that 0 is followed by 12. Because of this, it is convenient to make the "global_reset" condition equal to 12 also. While this is not necessary for the Verilog behavioural code, it simplifies the gate level implementation [why?].

        // 4-bit binary down-counter - of period 13
        module counter4_bit(q, d, decrement, load_data, global_reset, clock);

          // some appropriate declarations

        always @(posedge clock)
          if (global_reset)
            q = 12;
          else if (load_data)
            q = d;
          else if (decrement)
            begin
            if (q == 0)
              q = 12;
            else
              q = q - 1;
            end

        endmodule

Up-Down counter

If a counter has a period which is a power of two, it is simpler to design since the counter "wraps round" and the 'end" condition does not need to be explicitly detected. Thus for a four bit register, 15 + 1 = 0 and 0 - 1 = 15.

Below is the code for a 4-bit counter (with period 16) which can either count up or down according to an extra input signal.

        // 4-bit binary up-down-counter - of period 16
        module counter4_bit(q, d, updown, count, load_data, global_reset, clock);

          // some appropriate declarations

        always @(posedge clock)
          if (reset)
              q = 0;
          else if (load_data)
              q = d;
          else if (count)
              begin
              if (updown)
                  q = q + 1;
              else
                  q = q - 1;
              end

        endmodule

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