Always Block

Keywords: always

An always block is similar to the initial block, but the statements inside an always block will repeated continuously, in a looping fashion, until stopped by $finish or $stop.

Note: the $finish command actually terminates the simulation where as $stop. merely pauses it and awaits further instructions. Thus $finish is the preferred command unless you are using an interactive version of the simulator.

One way to simulate a clock pulse is shown in the example below. Note, this is not the best way to simulate a clock. See the section on the forever loop for a better method.

        module pulse;

        reg clock;

        initial clock = 1'b0; // start the clock at 0
        always #10 clock = ~clock; // toggle every 10 time units
        initial #5000 $finish // end the simulation after 5000 time units

        endmodule

EXERCISE
Using the initial and always constructs describe the wave for the following.

        reg clock;
        reg [1:0] alpha;