Summary
There are many different ways to write VHDL synthesizable models for combinational logic.
There is no 'best' way to write a model; for now, just use the statements/style that you feel most comfortable with and can get to work (of course!)
READ THE BOOK!!!!!!!!
- There is NO WAY that we can cover all possible examples in class. The book has many other VHDL examples.
- I have intentionally left out MANY, MANY language details. You can get by with what I have shown you, but feel free to experiment with other language features that you see discussed in the book or elsewhere.