VHDL for “dpathb” (cont)

architecture a of dpathb is

signal q,d: std_logic_vector (3 downto 0);

begin

point <= q; -- point register output

-- Flip flops for point register

stateff: process (clk,reset)

begin

if (reset = '1') then

q <= "0000";

elsif (clk'event and clk='1') then

q <= d;

end if;

end process stateff;

-- equations for D inputs of point register

d <= dicesum when (sp = '1') else q;

Note that ‘D’ is equal to dicesum when sp is asserted else keeps its same state - this is a register!!!

DFFs for point register