VHDL for “dpathb”

entity dpathb is

port ( clk,reset: in std_logic;

dicesum: in std_logic_vector(3 downto 0);

sp: in std_logic;

point: out std_logic_vector(3 downto 0);

eq: out std_logic;

d7_i: out std_logic;

d11_i: out std_logic;

d2312_i: out std_logic

);

end dpathb;

Entity (input/outputs) declaration

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