Digital Design Laboratory

Design and Implementation of a Digital Lock

(Finite State Machine Lab) 


Purpose

The purpose of this lab is:


Problem statement and specifications

You need to design a digital lock that has three input push-buttons: A, B and C. Assume that the buttons cannot be pressed simultaneously (an electromechanical interlock guarantees this). The lock should have the following features:

Use as few states as possible without compromising the operation or security of the lock. The project involves a considerable design component as well as implementation issues. In order to give yourself enough time to debug and implement the digital lock, you should start early and do most of the design work during the pre-lab.  A demo needs to be given to the lab assistant.


Pre-lab assignment:

Task one: Design of the Digital Lock FSM.
 

Task two:  One-pulse circuit.

As part of this task you will be concentrating on implementing and testing your design. This raises some interesting issues which are mainly related to timing. In your design you have assumed that when you press the push-button it will generate a single pulse which is synchronized with the clock. In reality this is not going to be the case unless you take special precautions. We are concerned with three issues:

  1. Pulse synchronization
  2. Generation of a single pulse when pressing the button.
1. One of the complications comes from the fact that the switch will not close synchronously with the clock edge so as to ensure proper set-up and hold times for the flip-flops to which the input is connected. Synchronization can be easily ensured by passing the input signal through a clocked D flip-flop.

2. A second problem comes from the fact that when one presses the push-button for a short moment, the time that the switch will be closed is usually much longer (msec range) than one clock period (microseconds or even nanoseconds). As a result, our digital lock (or any other finite state machine) will think that we are supplying a string of ones as the input. Thus, one needs to add a circuit after each push-button switch that will generate only one pulse every time that one presses the push-button, independent of the time one keeps the button pressed. Figure 1 shows the timing diagram.

Figure 1: Timing diagram: signal IN is generated asynchronously while signal X is a pulse that is in sync with the clock signal and lasts for only one clock period.


Notice that in Figure 1 the pulse X is synchronized with the falling edge of the clock. If one uses this pulse as the input to a finite state machine (or FF) that is clocked at the positive clock edge, one has ensured that the set-up and hold times will be respected.

The overall digital lock system is shown in Figure 2. It consists of the core FSM for the lock, together with the debouncing and one-pulse circuit for each push button input. The 7-segment LED is used to display the number of each state or the Alarm (A) and Unlock (U) states.
 
 


Figure 2: Schematic Block diagram of the Digital Lock system.





Design a circuit that generates a single pulse independent of the length of the input signal IN. You can assume that the clock period is much shorter than the time the input signal IN is asserted high. There are different methods to design such a circuit. One is an ad-hoc method where you are using your experience with flip-flops to come up with the circuit. An alternative method is more systematic and makes use of finite state machine design method. Indeed, the circuit we need to come up with can be considered as a finite state machine with one input and one output. In case you prefer the last method, you should give the state diagram, (or ASM), the transition table, the next state logic (assuming that you are using D flip-flops) and the schematic (flip-flops and gates). Notice that this circuit also takes care of the synchronization problem discussed above.

In summary, you need to design the following circuits as part of the pre-lab:


In-lab assignment:
 

A. Parts and Equipment:

B. Experiments

The goal is to implement, download, display and test the digital lock whose block diagram is shown in Figure 2. During the first task you will design and simulate  the finite state machines of  the digital lock and the synchronization (one-pulse) circuit. You will also design and simulate the debouncing circuit. As part of the second task, you will complete the top level schematic, simulate, and debug the overall circuit. Finally, you need to compile (implement) and download the  circuit on an FPGA or CPLD and test its operation. A demo needs to be given to the lab instructors..

Task one: Design of the digital lock FSM and a one-pulse circuit.

Task two: Top-level schematic. Task three: Implementation, downloading and testing.

Hand-in

You must hand in a lab report that contains the following:

The lab report is an important part of the laboratory. Write it carefully, be clear and well organized. It is the only way to convey that you did a great job in the lab. It is preferred (but not necessary) that you type the lab report.


References:

1. M. Mano and C. Kime, "Logic anc Computer Design Fundamentals," 2nd Edition, Prentice Hall, Upper Saddle River, NJ, 2001.
2. R. Katz, "Contemporary Logic Design", Benjamin/Cummings Publ., Reading, MA, 1994.
3. J. F. Wakerly, "Digital Design," 3rd edition, Prentice Hall, Upper Saddle River, NJ, 2000.
4. P. Horowitz and W. Hill, "The Art of Electronics", Cambridge University Press, Cambridge, 1989; p506.
5. XILINX XC4000 FPGA description.


Go to the Xilinx Foundation Tutorial

Copyright, 1999 Jan Van der Spiegel; Created by Jan Van der Spiegel; November 14, 1997; Updated November 14, 2001.