Pins of the XC95108 CPLD in a 84 PLCC package
and associated connections on the XESS XS95 Board
The following table lists the pins numbers and names for the 84 pin XC95108 CPLD and the accociated connections on the XS95 board.. For more information about the XC9500 CPLD devices, please consult the Xilinx website.
The pin numbering of the 84 pin FPGA is given in the following figure.
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Device: XC95108 No. of Macrocells: 108 Usable Gates: 2,400 fCNT.: 125 MHz Delay: tPD = 7.5ns pin-to-pin logic delays (see data book for more information) Programmable outputs: 24 mA drive, 3.3V or 5V I/O, slew rate control. JTAG Boundary scan support |
Figure 1: Pin numbering of the 84 pin PLCC
Table I: Pin number and corresponding connections on the XS95 board
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I/O | A4 (Address bit of the SRAM) |
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I/O | A7 (Address bit of the SRAM) |
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I/O | A5 (Address bit of the SRAM) |
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I/O | Free I/O 0 |
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I/0 | P1.3 |
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I/O | P1.0 (Port 1 of the microcontroller) and PC parallel port Control Output C0 |
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I/O | P1.1 |
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GND | |
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I/O /GCK1(Global CLK1) | CLK (from Programmable oscillator) |
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I/O /GCK2 | Output clock generated by the CPLD, connected to the clock input XTAL1 of the microcontroller. |
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I/O | P1.2 |
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I/O /GCK3 | Free I/O 1 |
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I/O | PSEN (program store enable) |
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I/O | 7-segment disp.-f (S5)/ Red1of VGA |
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I/O | 7-segment disp.-a (S6)/Hor SYNC of VGA |
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GND | |
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I/O | 7-segment disp.-g (S3)/ Green1of VGA |
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I/O | 7-segment disp.-b (S4)/ Red0 of VGA |
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I/O | 7-segment disp.-e (S2)/ Green0 of VGA |
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I/O | ALE (address latch enable pin) |
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I/O | 7-segment disp.-d (S0)/Blue0 of VGA |
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VCC | |
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I/O | 7-segment disp.-c (S1)/ Blue1 of VGA |
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I/O | 7-segment disp. - dec. pt/ Vert. SYNC of the VGA |
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I/O | Free I/O 2 |
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I/O | P3.4 (T0 - Timer 0) and KB_CLK of PS/2 |
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GND | |
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TDI (Test data in - for boundary scan) | P2.7( A15): Port P2.7 of microcontroller and addr. bit A15 of SRAM (only on the 128KB) |
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TMS (test mode) (for boundary scan) | ALE (address latch enable pin) |
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TCK (Test clock - for boundary scan) | |
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I/O | P3.0 (RXD) |
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I/O | P3.7 (/RD) |
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I/O | P3.5 (T1 - timer 1) |
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I/O | P2.7(A15).A15 |
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I/O | P0.7(AD7)/D7 (multiplexed address/data port and also conntected to data pin D7 of SRAM) |
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I/O | P0.6(A.D6)/D6 |
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I/O | P0.5(A.D5)/D5 |
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VCC | |
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I/O | P0.4(AD4)/D4 |
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I/O | P0.3(AD3)/D3 |
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I/O | P0.2(AD2)/D2 |
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GND | |
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I/O | P0.1(AD1)/D1 |
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I/O | P0.0(AD0)/D0 |
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I/O | RST (reset input of the microconroller) |
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I/O | Parallel port data output PC-D0 (can be used for clock signals - has an inverting Schmitt-trigger) |
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I/O | Parallel port data output PC-D1 (can be used for clock signals - has an inverting Schmitt-trigger) |
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I/O | Parallel port data output PC-D2 |
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GND | GND |
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I/O | Parallel port data output PC-D3 |
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I/O | Parallel port data output PC-D4 |
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I/O | Parallel port data output PC-D5 |
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I/O | P2.4(A12)/A12 (Port P2.4 of microcontroller and addr. bit A12 of SRAM |
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I/O | P2.2(A10)/A10 |
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I/O | P2.3(A11)/A11 |
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I/O | P2.1(A9).A9 |
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I/O | P2.5 (A13)/A13 |
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I/O | P2.0(A8)/A8 |
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TDO | |
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GND | |
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I/O | P2.6 (A14)/A14 |
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I/O | /OE (SRAM output enable pin) |
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I/O | P3.6 (/WR - data write) and /WE of SRAM |
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VCC | |
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I/O | /CE (SRAM chip enable) |
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I/O | P1.6 and parallel port PC-S5 |
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I/O | P1.7 |
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I/O | P3.3 (/INT1 - interrupt1) |
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I/O | P3.2 (/INT0 - interrupt0) |
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I/O | P3.1 (TXD), parallel Port PC-S6, KB_Data of PS/2 port |
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I/O | P1.5 and parallel port PC-S3 |
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I/O | P1.4 and parallel port PC-S4 |
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VCC | |
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I/O | A16 (Addr bit of SRAM) (For 128KB version) |
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I/O | A0 (Addr. bit of SRAM) |
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I/O | Free I/O 3 |
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I/O | Free I/O 4 |
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VCC | 5V |
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I/O | A1 (SRAM) |
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I/O | Parallel port data output PC-D7 |
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I/O | Parallel port data output PC-D6 |
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I/O | A2 (SRAM) |
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I/O | A6 (SRAM) |
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I/O | A3 (SRAM) |
References:
1. The Programmable Logic Data Book, Xilinx, San Jose, 1999. (http://www.xilinx.com/partinfo/databook.htm)
2. XS5, XSP Board V1.3 User Manual, XESS
Corp, Apex, 1999 (http://www.xess.com/xs95-manual-v1_3.pdf).
Created by Jan Van der Spiegel
<jan@ee.upenn.edu>;Updated June 12, 2000.