prepared by P. Bakowski

Contents: design units, primary design units, secondary design units, architectural modules, functional modules, structural modules, libraries, compilation-elaboration-simulation

Design units

The VHDL models are built from different kinds of units. There are two classes of VHDL design units : the primary design units and the secondary design units.

The primary design units are entity, package and configuration.

The secondary design units are architecture(s) and package body declaration.

The following pages contain a quick reference guide to the different kind of constructs used in VHDL. The references provide the formal syntax definition. The examples follow if you click on the formal definition images.

Primary design units - click on them

Packages define the interfaces(inputs & outputs) of common elements that may be visible to many designs. They contain the declarations of types, subprograms, components, files, aliases, attributes,...

Configuration unit is required if you construct a complex system assembled from several components (entities). It allows to select the required components from the specified library. (e.g. IEEE library). It may contain attribute specification, generate statemens, block and component configurations, ...

Entities are used to define the interface (inputs & outputs) to a given model plus the environment in which it is used. Basically, an entity contains generic and port clauses. The environment may contain types declaration , subprograms, constants, signals, file declarations, alias declarations, subropgram calls, assertions, ..

Secondary design units- click on them

The package body contains the functional bodies of procedures and functions that may be made visible to many models.

The architecture unit defines the functionality of a model, i.e. the relationship between inputs and outputs of a given model.

Note that more than one architecture may be associated to the same:

• architecture behavioral of entity_name is ...
• architecture data_flow of entity_name is ...
• architecture structural of entity_name is ...

Architectural modules

The architecture may be built from simple objects like variables or signals, sequential and concurrent assignments and from modules.

An architecture performs one or several concurrent activities. The execution/simulation of several concurrent activities requires the use of several processes. Each process is executed internally in a sequential way.

Note that a simplest concurrent statement is a signal assignment.

Complex architectures are constructed from modules.

We distinguish:

• the functional modules and
• the structural modules.

Functional modules

The functional modules are called subprograms.

We distinguish two kinds of subprograms:

• the functions
• the procedures.

Function/procedure declaration:

The function/procedure declarations describe the inputs and the outputs of a subprogram. Note that a function returns a single value specified by the return statement.

The function/procedure declarations are usually located in a package unit so that they may be shared by many models.

Function/procedure specification:

The function/procedure specifications describe the functionalities of a subprogram. Usually they are located in a package body unit so that they may be shared by many models.

Structural modules

The structural modules are called blocs.

The structural modules - blocks are incorporated into a given architecture. The block represent a portion of a design within an architecture body. Blocks may be hierarchcally nested to support design decomposition. The operation statements within the blocks may be controlled by the guard expression. Guard expression is of type boolean.

The functional modules - functions and procedures are usually declared and specified outside an architecture or a process; they are only called to perform the required sequential operations.

Libraries

A design library is used to store prevoiusly analyzed/compiled models These models or components are made visible to new designs by preceding the selected library name by library clause.

A library may contain one or more packages.

The elements of a library become available through the use clause. The designer may select the required packages and some or all elements from the indicated packages.

Compilation, elaboration and simulation

The simulation process of VHDL entities requires two preliminary steps:

• compilation
• simulation

The compilation consists in the analysis of the source description and the generation of an intermediary code stored in the design library.

There are several kinds of design libraries:

• work library; where the designer puts "by default" the compiled descriptions
• IEEE library; where the designer finds standard logic system and the corresponding types and functions
• user defined libraries; where the designer puts specific types of compiled components.

The next step is elaboration which performs several actions such as:

• hierarchical expansion of design hierarchy (components within components),
• elaboration of generics and declarative parts; this action creates a generic constant of the indicated type for each of the generics,
• binding of components; this action binds components to architectures,
• storage allocation of objects; this action allocates memory storage for the various objects,
• initialization values of objects; this action initializes the user defined values

The simulation process starts with several initializing actions such as:

• computation of explicit signals; the signals in ports and architectures are initialized, resolved and assigned values
• processes are executed until the suspension on an explicit or implicit wait statement
• simulation time is reset to 0 (now = 0 ns)

The following figure shows different elements and actions required before the simulation process can start.