aspect

VHDL based behavior modeling

prepared by P. Bakowski

Contents: introduction, design space cube, describing behaviour, discrete event time model, circuit type

Introduction

The objective of the behavioral modeling is to represent or to model the behavior of the component or system as seen from the utside. In general the modeling of behavior needs to express the functional and temporal aspects of the modeled objects.

Simple circuits may be modeled using small number of VHDL processes in one architectural unit. Complex circuits or systems must be decomposed into several entities, each one built from several processes.

If possible, behavioral modeling exploits abstract types and values and high-level operators such as integer additions and multiplications. The usage of these operators depends however on the inherent complexity and nature of the modeled component or system.

In the following pages we are going first to model small complexity circuits.Below we recall the description domains and abstraction levels for VHDL

The hardware may be designed and described along several aspects or domains:

the functional domain,

the structural domain, and

the temporal domain.

Then the domains may be presented at different abstraction levels, such as:

At these different abstraction levels the time may be perceived as:

The information may be perceived:

Among the models best suited to express the decriptional capacities of VHDL is the Design Cube Model presented by W. Ecker and M.Hofmeister [Euro-VHDL'92]

The design cube model is built on three dimensional design space involving the (1) specification view (structure, data-flow, behavior), the timing (propagation delay - continuous time, clock related - discrete time, and time causality - before after), and the value abstraction (bit values, composite bit values, abstract values).

Design space cube (W. Ecker)

Using the "design cube" 27 of different levels of temporal and functional abstraction may be identified. Only few of them have well established meaning.

Abstract or algorithmic models are built from: behavioral specification, time causality, and abstract values.

Register Transfer models are build upon data flows, clock related synchronization, and composite bit values.

Finally logic level models are mainly structural, with propagation delays, and bit values.

Describing behaviour

In many cases, it is not appropriate to describe a module structurally. One such case is a module which is at the bottom of the hierarchy of some other structural description.

For example, if you are designing a system using IC packages bought from an IC shop, you do not need to model the internal structure of an IC. In such cases, a description of the function performed (behavior) by the module is required, without reference to its actual internal structure.

Such a description is called a functional or behavioral description.

More complex behaviours cannot be described purely as a function of inputs. In systems with feedback, the outputs are also a function of time.

VHDL solves this problem by allowing description of behaviour in the form of a simulatable model.

Discrete event time model

Once the behaviour of a module have been specified, it is possible to simulate the module by executing its bevioural description.

This is done by simulating the passage of time in discrete steps.

At some simulation time, a module input may be stimulated by changing the value on an input port.

The module reacts by running the code of its behavioural description and scheduling new values to be placed on the signals connected to its output ports at some later simulated time.

This is called scheduling a transaction on that signal.

If the new value is different from the previous value on the signal, an event occurs, and other modules with input ports connected to the signal may be activated.

The simulation starts with an initialisation phase, and then proceeds by repeating a two- stage simulation cycle .

In the initialisation phase, all signals are given initial values, the simulation time is set to zero, and each module's behaviour program is executed. This usually results in transactions being scheduled on output signals for some later time. In the first stage of a simulation cycle, the simulated time is advanced to the earliest time at which a transaction has been scheduled. All transactions scheduled for that time are executed, and this may cause events to occur on some signals.

In the second stage, all modules which react to events occurring in the first stage have their behaviour program executed. These programs will usually schedule further transactions on their output signals. When all of the behaviour programs have finished executing, the simulation cycle repeats. If there are no more scheduled transactions, the whole simulation is completed.

The purpose of the simulation is to gather information about the changes in system state over time. This can be done by running the simulation under the control of a simulation monitor . The monitor allows signals and other state information to be viewed or stored in a trace file for later analysis. It may also allow interactive stepping of the simulation process, much like an interactive program debugger.

Type of circuit

The beavioral modeling exploits a number of techniques that are highely dependent on the nature and complexity of the circuit.

The following is a simple list of circuit types ordered according to the growing complexity: